ICS348
Quad PLL Field Programmable VersaClock Synthesizer
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Output Frequency Synthesis
Error
Power-up time
Symbol
F
IN
Conditions
Fundamental Crystal
Input Clock
VDD=3.3 V
Min.
5
2
0.25
Typ.
Max. Units
27
50
200
MHz
MHz
MHz
ns
ns
60
%
ppm
10
2
ms
ms
ps
ps
250
ps
t
OR
t
OF
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
Configuration Dependent
PLL lock-time from
power-up, Note 3
PDTS goes high until
stable CLK output, Note 3
40
1
1
49-51
TBD
3
0.2
50
+200
-250
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Pin-to-Pin Skew
Note 1: Measured with 15 pF load.
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
Low Skew Outputs
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
135
93
78
60
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 348 H
Integrated Circuit Systems, Inc.
●
6
525 Race Street, San Jose, CA 95126
●
Revision 051705
tel (408) 297-1201
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www.icst.com
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