Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
Type
Power
Output
Output
Power
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pulldown
Description
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inver ting differential clock input.
Non-inver ting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6, 12,
25, 31, 36
2, 3
4, 5
7, 17, 20,
30, 41, 44
8, 9
10, 11
13, 14
15, 16
18
19
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
Name
V
DD
nQ5, Q5
nQ4, Q4
GND
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
CLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
Differential output pair. LVDS interface levels.
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15;
OE1 controls outputs Q0, nQ0 thru Q7, nQ7.
42, 43
OE2, OE1
Input
Pullup
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
45, 46
nQ7, Q7
Output
47, 48
nQ6, Q6
Output
Differential output pair. LVDS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8516FY
www.icst.com/products/hiperclocks.html
2
REV. A JULY 30, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
