Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
Test Conditions
Minimum
250
1.125
-10
-1
Typical
400
1.4
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
∆
V
OD
V
OS
∆
V
OS
I
OZ
I
OFF
I
OSD
I
OS
/I
OSB
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Shor t Circuit Current
Output Shor t Circuit Current
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
20% to 80%
100
45
50
1.6
2.0
Test Conditions
Minimum
Typical
Maximum
700
2.4
90
500
550
55
5
5
Units
MHz
ns
ps
ps
ps
%
ns
ns
t
sk(o)
t
sk(pp)
t
R
/t
F
o dc
t
PZL
, t
PZH
t
PLZ
, t
PHZ
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8516FY
www.icst.com/products/hiperclocks.html
5
REV. A JULY 30, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
