Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
Test Conditions
Minimum
700
20% to 80%
ƒ
≤
150MHz
150 < ƒ
≤
250MHz
150
48
46
Typical
Maximum
350
1075
375
800
52
54
Units
MHz
ps
ps
ps
%
%
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
250 < ƒ
≤
350MHz
45
55
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
150MHz
150
48
700
Test Conditions
Minimum
Typical
Maximum
350
1200
475
800
52
Units
MHz
ps
ps
ps
%
150 < ƒ
≤
350MHz
46
54
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85222AM-01
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4
REV. A NOVEMBER 15, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
