Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
CLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Disabled
nCLK, nPCLK
CLK, PCLK
Enabled
CLK_EN
nQ0 - nQ3
Q0 - Q3
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
nCLK or nPCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
LOW
HIGH
LOW
HIGH
HIGH
Outputs
Q0 thru Q3
nQ0 thru nQ3
HIGH
LOW
HIGH
LOW
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential
input to accept single ended levels.
8523BG
www.icst.com/products/hiperclocks.html
3
REV. B JULY 31, 2001
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
