Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and
V
CMR
input requirements.
Figures 5A to 5E
show interface
examples for the HiPerClockS PCLKx/nPCLKx input driven
by the most common driver types. The input interfaces sug-
3.3V
3.3V
3.3V
R1
50
CML
Zo = 50 Ohm
PCLK
Zo = 60 Ohm
2.5V
2.5V
3.3V
R3
120
SSTL
Zo = 60 Ohm
PCLK
R4
120
R2
50
Zo = 50 Ohm
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
F
IGURE
5A. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY A
CML D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY AN
SSTL D
RIVER
3.3V
3.3V
3.3V
R3
125
Zo = 50 Ohm
PCLK
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
R2
84
HiPerCloc kS
Input
Zo = 50 Ohm
R5
100
C2
3.3V
3.3V
R4
125
3.3V
Zo = 50 Ohm
LVDS
C1
R3
1K
R4
1K
PCLK
nPCLK
HiPerClockS
PC L K/n PCL K
R1
1K
R2
1K
F
IGURE
5C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY A
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY A
3.3V LVDS D
RIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3
84
R4
84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
F
IGURE
5E. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY A
3.3V LVPECL D
RIVER WITH
AC C
OUPLE
853014BG
www.icst.com/products/hiperclocks.html
10
REV. C MAY 13, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
