Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
put is driven by an LVPECL driver. CLK_SEL is set at logic high
to select PCLK1/nPCLK1 input.
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS853014 LVPECL buffer.
Figure 6
shows a schematic example
of the ICS853014 LVPECL clock buffer. In this example, the in-
Zo = 50
+
Zo = 50
-
R2
50
R1
50
3.3V
R12
3.3V
Zo = 50
3.3V
Zo = 50
C2
0.1u
LVPECL Driv er
R9
50
R10
50
C1
0.1u
1K
11
12
13
14
15
16
17
18
19
3.3V
20
U1
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
nEN
VCC
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
R3
50
C3
0.1u
Zo = 50
+
Zo = 50
ICS853014
R5
50
R4
50
-
C5
0.1u
R7
50
R11
1K
R6
50
C4
0.1u
F
IGURE
6. E
XAMPLE
ICS853014 LVPECL C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
853014BG
www.icst.com/products/hiperclocks.html
11
REV. C MAY 13, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
