Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
Type
Description
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage.
Pulldown Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11
12
13
14
15
16
17
18, 20
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
EE
CLK_SEL
PCLK0
nPCLK0
V
BB
PCLK1
nPCLK1
V
CC
Output
Output
Output
Output
Output
Power
Input
Input
Input
Output
Input
Input
Power
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
19
nEN
Input
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
kΩ
kΩ
853014BG
www.icst.com/products/hiperclocks.html
2
REV. C MAY 13, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
