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IC42S16100-6T 参数 Datasheet PDF下载

IC42S16100-6T图片预览
型号: IC42S16100-6T
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×16位×2组( 16兆位)同步动态RAM [512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 78 页 / 802 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC42S16100  
OPERATION COMMAND TABLE(1,2)  
Current State Command  
Operation  
CS RAS CAS WE A11 A10 A9-A0  
Write With  
DESL  
Burst Write Continues, Write Recovery And Precharge  
H
X
X
X
X
X
X
Auto-Precharge  
When Done  
NOP  
BST  
Burst Write Continues, Write Recovery And Precharge  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
X
X
V
V
V
V
X
X
X
X
Illegal  
X
(18)  
READ/READA  
WRIT/WRITA  
ACT  
PRE/PALL  
REF/SELF  
MRS  
Illegal  
V
V
V
V
(18)  
(18)  
Illegal  
L
V
Illegal(10)  
H
H
L
V
Illegal(10)  
L
V
X
X
Illegal  
Illegal  
L
X
L
L
OPCODE  
Row Precharge DESL  
No Operation, Idle State After tRP Has Elapsed  
X
H
H
H
H
L
X
H
H
L
X
X
X
V
V
V
V
X
X
X
X
X
NOP  
BST  
READ/READA  
WRIT/WRITA  
ACT  
No Operation, Idle State After tRP Has Elapsed  
X
No Operation, Idle State After tRP Has Elapsed  
X
Illegal(10)  
V
V
V
V
(18)  
Illegal(10)  
L
V
(18)  
(18)  
Illegal(10)  
H
H
L
V
PRE/PALL  
REF/SELF  
MRS  
No Operation, Idle State After tRP Has Elapsed(10)  
L
V
X
X
X
Illegal  
Illegal  
L
H
L
L
L
OP CODE  
Immediately  
Following  
Row Active  
DESL  
No Operation, Row Active After tRCD Has Elapsed  
H
X
X
X
X
X
X
X
X
X
NOP  
No Operation, Row Active After tRCD Has Elapsed  
L
H
H
H
X
BST  
No Operation, Row Active After tRCD Has Elapsed  
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
V
V
V
V
X
X
Illegal(10)  
Illegal(10)  
Illegal(10,14)  
Illegal(10)  
Illegal  
V
V
(18)  
READ/READA  
WRIT/WRITA  
ACT  
(18)  
L
V
V
V
(18)  
H
H
L
H
L
V
PRE/PALL  
REF/SELF  
MRS  
L
V
X
X
L
H
L
X
Illegal  
L
L
OP CODE  
Write  
DESL  
No Operation, Row Active After tDPL Has Elapsed  
H
X
X
X
X
X
X
X
X
X
Recovery  
NOP  
No Operation, Row Active After tDPL Has Elapsed  
L
H
H
H
X
BST  
No Operation, Row Active After tDPL Has Elapsed  
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
V
V
V
V
X
X
(18)  
READ/READA  
WRIT/WRITA  
ACT  
Read Start  
Write Restart  
Illegal(10)  
Illegal(10)  
Illegal  
V
V
(18)  
L
V
V
V
(18)  
H
H
L
H
L
H
L
V
PRE/PALL  
REF/SELF  
MRS  
L
V
X
X
L
X
Illegal  
L
L
OP CODE  
Integrated Circuit Solution Inc.  
15  
DR024-0D 06/25/2004