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IC42S16100-6T 参数 Datasheet PDF下载

IC42S16100-6T图片预览
型号: IC42S16100-6T
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×16位×2组( 16兆位)同步动态RAM [512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 78 页 / 802 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC42S16100
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Symbol Parameter
t
CAC
t
RCD
t
RAC
t
RC
t
RAS
t
RP
t
RRD
t
CCD
t
DPL
t
DAL
t
RBD
t
WBD
t
RQL
t
WDL
t
PQL
t
QMD
t
DMD
t
MCD
Clock Cycle Time
Operating Frequency
CAS
Latency
Active Command To Read/Write Command Delay Time
RAS
Latency (t
RCD
+ t
CAC
)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
Column Command Delay Time
(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay Time
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
-5
5
200
3
3
6
10
6
3
2
1
2
5
3
0
3
0
–2
2
0
2
-6
6
166
3
3
6
10
6
3
2
1
2
5
3
0
3
0
–2
2
0
2
-7
7
143
3
3
6
10
6
3
2
1
2
5
3
0
3
0
–2
2
0
2
Units
ns
MHz
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
AC TEST CONDITIONS
(Input/Output Reference Level: 1.4V)
Input
t
CHI
2.4V
t
CK
t
CL
CLK
1.4V
0.4V
t
CS
2.4V
t
CH
INPUT
1.4V
0.4V
t
OH
OUTPUT
1.4V
t
AC
1.4V
Output Load
I/O
Z
O
= 50Ω
50
+1.4V
30 pF
8
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004