欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICS8442AYLF 参数 Datasheet PDF下载

ICS8442AYLF图片预览
型号: ICS8442AYLF
PDF下载: 下载PDF文件 查看货源
内容描述: 700MHZ ,晶体振荡器,差分LVDS频率合成器 [700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER]
分类和应用: 振荡器晶体振荡器外围集成电路时钟
文件页数/大小: 15 页 / 284 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS8442AYLF的Datasheet PDF文件第2页浏览型号ICS8442AYLF的Datasheet PDF文件第3页浏览型号ICS8442AYLF的Datasheet PDF文件第4页浏览型号ICS8442AYLF的Datasheet PDF文件第5页浏览型号ICS8442AYLF的Datasheet PDF文件第6页浏览型号ICS8442AYLF的Datasheet PDF文件第7页浏览型号ICS8442AYLF的Datasheet PDF文件第8页浏览型号ICS8442AYLF的Datasheet PDF文件第9页  
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
F
EATURES
Dual differential LVDS outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
Output frequency range: 31.25MHz to 700MHz
Crystal input frequency range: 10MHz to 25MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 2.7ps (typical)
Cycle-to-cycle jitter: 18ps (typical)
3.3V supply voltage
0°C to 85°C ambient operating temperature
“Lead-Free” package available
G
ENERAL
D
ESCRIPTION
The ICS8442 is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClock ™
S
family of High Performance Clock Solutions from
ICS. The ICS8442 has a selectable TEST_CLK
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The
VCO operates at a frequency range of 250MHz to 700MHz. The
VCO frequency is programmed in steps equal to the value of
the input reference or crystal frequency. The VCO and output
frequency can be programmed using the serial or parallel inter-
face to the configuration logic. The low phase noise characteris-
tics of the ICS8442 makes it an ideal clock source for Gigabit
Ethernet and Sonet applications.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL2
M4
M3
M2
M1
M0
XTAL_SEL
TEST_CLK
XTAL1
OSC
XTAL2
0
32 31 30 29 28 27 26 25
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
DD
FOUT1
nFOUT1
V
DD
FOUT0
nFOUT0
GND
24
23
22
XTAL1
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
1
÷
2
÷
4
÷
8
N0
N1
nc
FOUT0
nFOUT0
FOUT1
nFOUT1
ICS8442
21
20
19
18
17
VCO
÷
M
0
1
GND
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8442AY
www.icst.com/products/hiperclocks.html
1
REV. C JULY 8, 2004