Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but
does not effect loaded M, N, and T values.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
275
•
•
650
675
M Divide
10
11
•
•
26
27
256
M8
0
0
•
•
0
0
128
M7
0
0
•
•
0
0
64
M6
0
0
•
•
0
0
32
M5
0
0
•
•
0
0
16
M4
0
0
•
•
1
1
8
M3
1
1
•
•
1
1
4
M2
0
0
•
•
0
0
2
M1
1
1
•
•
1
1
1
M0
0
1
•
•
0
1
0
700
28
0
0
0
0
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
250
125
62.5
31.25
Maximum
700
350
175
87.5
8442AY
www.icst.com/products/hiperclocks.html
4
REV. C JULY 8, 2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
