IS61C632A
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
t
KC
t
KH
t
KL
t
KQ
t
KQX
(2)
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
-4
Min. Max.
8
4
4
—
1.5
0
1.5
—
0
0
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
25
—
—
—
4
—
—
4
4
—
—
4.5
—
—
—
—
—
—
—
—
—
—
—
-5
Min. Max.
10
4
4
—
1.5
0
1.5
—
0
0
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
5
—
—
5
5
—
—
4.8
—
—
—
—
—
—
—
—
—
—
—
-6
Min. Max.
12
4
4
—
2
0
2
—
0
0
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
45
—
—
—
6
—
—
6
6
—
—
6
—
—
—
—
—
—
—
—
—
—
—
-7
Min. Max.
13
6
6
—
2
0
2
—
0
0
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
—
—
7
—
—
6
6
—
—
6
—
—
—
—
—
—
—
—
—
—
-8
Min. Max. Unit
15
6
6
—
2
0
2
—
0
0
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
80
—
—
—
8
—
—
6
6
—
—
6
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
t
KQHZ
(2,3)
Clock High to Output High-Z
t
OEQ
t
OEQX
(2)
Output Enable to Output Valid
Output Disable to Output Invalid
t
OELZ
(2,3)
Output Enable to Output Low-Z
t
OEHZ
(2,3)
Output Disable to Output High-Z
t
AS
t
SS
t
WS
t
CES
t
AVS
t
AH
t
SH
t
WH
t
CEH
t
AVH
t
CFG
Address Setup Time
Address Status Setup Time
Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup
(1)
66.7 —
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
8
Integrated Circuit Solution Inc.
SSR001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
