IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1, 3)
t
RC
ADDRESS
t
AA
t
OH
OE
t
OE
CS
t
OHZ (5)
t
OLZ (5)
t
ACS
t
CLZ (5)
t
CHZ
(5)
DATA
OUT
I
CC
V
CC
Supply
Currents
I
SB
t
PU
DATA
VALID
t
PD
3089 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
3089 drw 07
t
OH
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
CS
t
CLZ (5)
DATA
OUT
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±500mV
from steady state.
t
ACS
t
CHZ
DATA VALID
(5)
3089 drw 08
5.1
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
