IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
WE
CONTROLLED TIMING)
t
WC
ADDRESS
t
AW
CS
(1, 2, 5, 7)
t
AS
WE
t
WP(7)
t
WR
(3)
t
CHZ (6)
t
WHZ
DATA
OUT
PREVIOUS DATA VALID
(4)
(6)
t
OW
t
DW
t
DH
(6)
DATA
(4)
VALID
DATA
IN
DATA VALID
3089 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CS
CONTROLLED TIMING)
(1, 2, 3, 5, 7)
t
WC
ADDRESS
t
AW
CS
t
WR
t
AS
t
CW
(3)
WE
t
DW
DATA
IN
DATA VALID
t
DH
3089 drw 10
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured
±500mV
from steady state.
7.
OE
is continuously HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the
I/O drivers to turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not
apply and the write pulse is the specified t
WP
. For a
CS
controlled write cycle,
OE
may be LOW with no degradation to t
CW
.
5.1
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
