IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
R/W
DATAOUT
BUSYOUT
t
OH
(1)
t
LZ
(4)
VALID DATA
(2)
t
HZ
(3, 4)
t
BDD
2738 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDDdelayisrequiredonlyincaseswheretheoppositeportiscompletingawriteoperationtothesameaddresslocation. Forsimultaneous readoperations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
t
PU
tPD
I
CC
SB
50%
50%
I
2738 drw 08
6.06
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
