欢迎访问ic37.com |
会员登录 免费注册
发布采购

IDT71321SA55J 参数 Datasheet PDF下载

IDT71321SA55J图片预览
型号: IDT71321SA55J
PDF下载: 下载PDF文件 查看货源
内容描述: HIGH -SPEED 2K ×8双端口静态对中断RAM [HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 16 页 / 255 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号IDT71321SA55J的Datasheet PDF文件第3页浏览型号IDT71321SA55J的Datasheet PDF文件第4页浏览型号IDT71321SA55J的Datasheet PDF文件第5页浏览型号IDT71321SA55J的Datasheet PDF文件第6页浏览型号IDT71321SA55J的Datasheet PDF文件第8页浏览型号IDT71321SA55J的Datasheet PDF文件第9页浏览型号IDT71321SA55J的Datasheet PDF文件第10页浏览型号IDT71321SA55J的Datasheet PDF文件第11页  
IDT7132SA/LA and IDT 7142SA/LA  
High Speed 2K x 8 Dual Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
AC Electrical Characteristics Over the  
Operating Temperature and Supply Voltage Range(3,5)  
7132X20(2)  
7142X20(2)  
Com'l Only  
7132X25(2)  
7132X35  
7142X35  
Com'l &  
Military  
7142X25(2)  
Com'l, Ind  
& Military  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
____  
____  
____  
t
RC  
AA  
ACE  
AOE  
OH  
LZ  
HZ  
PU  
PD  
Read Cycle Time  
20  
25  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
t
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
20  
20  
25  
25  
35  
35  
____  
____  
____  
____  
____  
____  
t
t
11  
12  
20  
____  
____  
____  
t
Output Hold from Address Change  
Output Low-Z Time (1,4)  
3
3
3
____  
____  
____  
t
0
0
0
Output High-Z Time(1,4)  
10  
10  
15  
____  
____  
____  
t
t
Chip Enable to Power Up Time(4)  
Chip Disable to Power Down Time(4)  
0
0
0
____  
____  
____  
____  
____  
____  
t
20  
25  
35  
ns  
2692 tbl 08a  
7132X55  
7132X100  
7142X55  
Com'l &  
Military  
7142X100  
Com'l &  
Military  
Symbol  
READ CYCLE  
Parameter  
Min.  
Max.  
Min.  
Max.  
Unit  
____  
____  
t
RC  
AA  
ACE  
AOE  
OH  
LZ  
HZ  
PU  
PD  
Read Cycle Time  
55  
100  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
t
Address Access Time  
55  
55  
100  
100  
____  
____  
____  
____  
t
Chip Enable Access Time  
Output Enable Access Time  
Output Hold from Address Change  
Output Low-Z Time(1,4)  
t
25  
40  
____  
____  
t
3
10  
____  
____  
t
5
5
Output High-Z Time(1,4)  
25  
40  
____  
____  
t
t
Chip Enable to Power Up Time(4)  
Chip Disable to Power Down Time(4)  
0
0
____  
____  
____  
____  
t
50  
50  
ns  
2692 tbl 08b  
NOTES:  
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).  
2. PLCC package only.  
3. 'X' in part numbers indicates power rating (SA or LA).  
4. This parameter is guaranteed by device characterization, but is not production tested.  
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.  
7
6.42