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IDT71321SA55J 参数 Datasheet PDF下载

IDT71321SA55J图片预览
型号: IDT71321SA55J
PDF下载: 下载PDF文件 查看货源
内容描述: HIGH -SPEED 2K ×8双端口静态对中断RAM [HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 16 页 / 255 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7132SA/LA and IDT 7142SA/LA  
High Speed 2K x 8 Dual Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
AC Electrical Characteristics Over the  
Operating Temperature Supply Voltage Range(5,6)  
7132X20(2)  
7142X20(2)  
Com'l Only  
7132X25(2)  
7142X25(2)  
Com'l, Ind  
& Military  
7132X35  
7142X35  
Com'l &  
Military  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
WRITE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
EW  
AW  
AS  
WP  
WR  
DW  
HZ  
DH  
WZ  
OW  
Write Cycle Time(3)  
20  
15  
15  
0
25  
20  
20  
0
35  
30  
30  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Chip Enable to End-of-Write  
Address Valid to End-of-Write  
Address Set-up Time  
Write Pulse Width(4)  
t
t
t
15  
0
15  
0
25  
0
t
Write Recovery Time  
Data Valid to End-of-Write  
Output High-Z Time(1)  
Data Hold Time  
t
10  
12  
15  
____  
____  
____  
t
10  
10  
15  
____  
____  
____  
t
0
0
0
____  
____  
____  
t
Write Enable to Output in High-Z(1)  
Output Active from End-of-Write(1)  
10  
10  
15  
____  
____  
____  
t
0
0
0
ns  
2692 tbl 09  
7132X55  
7132X100  
7142X55  
Com'l &  
Military  
7142X100  
Com'l &  
Military  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Unit  
WRITE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
EW  
AW  
AS  
WP  
WR  
DW  
HZ  
DH  
WZ  
OW  
Write Cycle Time(3)  
55  
40  
40  
0
100  
90  
90  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Chip Enable to End-of-Write  
Address Valid to End-of-Write  
Address Set-up Time  
t
t
t
Write Pulse Width(4)  
30  
0
55  
0
t
Write Recovery Time  
t
Data Valid to End-of-Write  
Output High-Z Time(1)  
20  
40  
____  
____  
t
25  
40  
____  
____  
t
Data Hold Time  
0
0
____  
____  
t
Write Enable to Output in High-Z(1)  
Output Active from End-of-Write(1)  
30  
40  
____  
____  
t
0
0
ns  
2692 tbl 10  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization  
but is not production tested.  
2. PLCC package only.  
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.  
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the  
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.  
5. 'X' in part numbers indicates power rating (SA or LA).  
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.  
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