IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(7,8)
7132X20
(1)
7142X20
(1)
Com'l Only
Symbol
BUSY
Timing (For Master IDT7132 Only)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
WH
t
DDD
t
APS
t
BDD
BUSY
Access Time from Address
BUSY
Disable Time from Address
BUSY
Access Time from Chip Enable
BUSY
Disable Time from Chip Enable
Write Pulse to Data Delay
(2)
Write Hold After
BUSY
(6)
Write Data Valid to Read Data Delay
(2)
Arbitration Priority Set-up Time
(3)
BUSY
Disable to Valid Data
(4)
____
____
____
____
____
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
Min.
Max.
7132X35
7142X35
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
20
20
20
20
50
____
____
____
____
____
____
20
20
20
20
50
____
____
____
____
____
____
20
20
20
20
60
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
____
15
____
20
____
35
____
35
____
35
____
5
____
5
____
5
____
25
35
35
BUSY
Timing (For Slave IDT7142 Only)
t
WB
t
WH
t
WDD
t
DDD
Write to
BUSY
Input
(5)
Write Hold After
BUSY
(6)
Write Pulse to Data Delay
(2)
Write Data Valid to Read Data Delay
(2)
0
12
____
____
____
____
0
15
____
____
____
____
0
20
____
____
____
____
ns
ns
ns
ns
2692 tbl 11a
40
30
50
35
60
35
7132X55
7142X55
Com'l &
Military
Symbol
BUSY
Timing (For Master IDT7132 Only)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
WH
t
DDD
t
APS
t
BDD
BUSY
Access Time from Address
BUSY
Disable Time from Address
BUSY
Access Time from Chip Enable
BUSY
Disable Time from Chip Enable
Write Pulse to Data Delay
(2)
Write Hold After
BUSY
(6)
Write Data Valid to Read Data Delay
(2)
Arbitration Priority Set-up Time
(3)
BUSY
Disable to Valid Data
(4)
____
____
____
____
____
7132X100
7142X100
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
30
30
30
30
80
____
____
____
____
____
____
50
50
50
50
120
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
____
20
____
55
____
100
____
5
____
5
____
50
65
BUSY
Timing (For Slave IDT7142 Only)
t
WB
t
WH
t
WDD
t
DDD
Write to
BUSY
Input
(5)
Write Hold After
BUSY
(6)
Write Pulse to Data Delay
(2)
Write Data Valid to Read Data Delay
(2)
0
20
____
____
____
____
0
20
____
____
____
____
ns
ns
ns
ns
2692 tbl 11b
80
55
120
100
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
