IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side
(1)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
BUSY
OUT
t
BDDH
(2,3)
2692 drw 07
t
OH
DATA VALID
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2, Either Side
(1)
t
ACE
CE
t
AOE
(3)
OE
t
LZ
(4)
DATA
OUT
t
LZ
(4)
I
CC
CURRENT
I
SS
t
PU
50%
VALID DATA
t
PD
(3)
50%
2692 drw 08
t
HZ
(5)
t
HZ
(5)
NOTES:
1. R/W = V
IH,
CE
= V
IL,
and is
OE
= V
IL.
Address is valid prior to the coincidental with
CE
transition LOW.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations,
BUSY
has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
4. Timing depends on which signal is asserted last,
OE
or
CE.
5. Timing depends on which signal is de-asserted first,
OE
or
CE.
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
