IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A
0
X
A
1
X
X
A
2
A
3
A
4
R/
W
H
X
H
X
X
H
H
H
ADV/
LD
L
X
L
X
X
L
L
L
CE
(2)
L
X
L
X
X
L
L
L
CEN
L
H
L
H
H
L
L
L
BW
x
X
X
X
X
X
X
X
X
OE
X
X
X
L
L
L
L
L
I/O
X
X
X
Q
0
Q
0
Q
0
Q
1
Q
2
Comments
Address and Control meet setup
Clock n+1 Ignored
Clock Valid
Clock Ignored. Data Q
0
is on the bus.
Clock Ignored. Data Q
0
is on the bus.
Address A
0
Read out (bus trans.)
Address A
1
Read out (bus trans.)
Address A
2
Read out (bus trans.)
4875 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
Write Operation with Clock Enable Used
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A
0
X
A
1
X
X
A
2
A
3
A
4
R/
W
L
X
L
X
X
L
L
L
ADV/
LD
L
X
L
X
X
L
L
L
CE
(2)
L
X
L
X
X
L
L
L
CEN
L
H
L
H
H
L
L
L
BW
x
L
X
L
X
X
L
L
L
OE
X
X
X
X
X
X
X
X
I/O
X
X
X
X
X
D
0
D
1
D
2
Comments
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
Clock Ignored.
Clock Ignored.
Write Data D
0
Write Data D
1
Write Data D
2
4875 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
6.42
13
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
