IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
CEN
L
L
L
L
L
L
H
R/
W
L
H
X
X
X
X
X
Chip
(5)
Enable
Select
Select
X
X
Deselect
X
X
ADV/
LD
L
L
H
H
L
H
X
BW
x
Valid
X
Valid
X
X
X
X
ADDRESS
USED
External
External
Internal
Internal
X
X
X
PREVIOUS CYCLE
X
X
LOAD WRITE /
BURST WRITE
LOAD READ /
BURST READ
X
DESELECT / NOOP
X
CURRENT CYCLE
LOAD WRITE
LOAD READ
BURST WRITE
(Advance burst counter)
(2)
BURST READ
(Advance burst counter)
(2)
DESELECT or STOP
(3)
NOOP
SUSPEND
(4)
I/O
(2 cycles later)
D
(7)
Q
(7)
D
(7)
Q
(7)
HiZ
HiZ
Previous Value
4875 tbl 08
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE
1
, or
CE
2
is sampled high or CE
2
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires
CE
1
= L,
CE
2
= L, CE
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes
(1)
OPERATION
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
NO WRITE
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
R/
W
H
L
L
L
L
L
L
BW
1
X
L
L
H
H
H
H
BW
2
X
L
H
L
H
H
H
BW
3
(3)
X
L
H
H
L
H
H
BW
4
(3)
X
L
H
H
H
L
H
4875 tbl 09
6.42
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
