IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
3026 tbl 08
Data Retention Waveform
DATA RETENTION MODE
V
DR
≥
2.0V
V
CC
3.0V
t
CDR
3.0V
t
R
CE
V
IH
V
DR
V
IH
3026 drw 04
,
3.3V
590Ω
DATA
OUT
BUSY
INT
435Ω
DATA
OUT
30pF
435Ω
3.3V
590Ω
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(2)
71V321X25
71V421X25
Com 'l
& Ind
Sym bol
READ CYCLE
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
25
____
____
____
____
71V321X35
71V421X35
Com 'l Only
Min.
Max.
71V321X55
71V421X55
Com 'l Only
Min.
Max.
Unit
Param eter
Min.
Max.
35
____
____
____
____
55
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
3026 tbl 09
25
25
12
____
____
35
35
20
____
____
55
55
25
____
____
3
0
____
3
0
____
3
0
____
12
____
15
____
30
____
0
____
0
____
0
____
50
50
50
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
5
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
