IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side
(1)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
BUSY
OUT
t
BDD
(2,3)
3026 drw 06
t
OH
DATA VALID
PREVIOUS DATA VALID
NOTES:
1. R/W = V
IH
,
CE
= V
IL
, and is
OE
= V
IL
. Address is valid prior to the coincidental with
CE
transition LOW.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
Timing Waveform of Read Cycle No. 2, Either Side
(3)
t
ACE
CE
t
AOE
OE
t
LZ
(1)
DATA
OUT
t
LZ
I
CC
CURRENT
I
SS
t
PU
50%
(1)
(4)
t
HZ
(2)
t
HZ
VALID DATA
t
PD
(4)
(2)
50%
3026 drw 07
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE.
2. Timing depends on which signal is de-asserted first,
OE
or
CE.
3. R/W = V
IH
and the address is valid prior to or coincidental with
CE
transition LOW.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
6
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
