IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ
(5)
(5)
(3)
t
ACS
t
CLZ
DATA
OUT
t
CHZ (5)
t
OHZ (5)
HIGH IMPEDANCE
DATA
OUT
VALID
t
PD
V
CC
SUPPLY I
CC
CURRENT I
SB
t
PU
3622 drw 06
Timing Waveform of Read Cycle No. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3622 drw 07
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
6.42
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
