3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
Features
◆
◆
IDT71V124
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-
nized as 128K x 8. It is fabricated using IDT’s high-performance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs. The JEDEC center
power/GND pinout reduces noise generation and improves system
performance.
The IDT71V124 has an output enable pin which operates as fast as
7ns, with address access times as fast as 15ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.
◆
◆
◆
◆
◆
◆
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Commercial (0°C to +70°C) and Industrial (–40°C to
+85°C) temperature options
Equal access and cycle times
— Industrial and Commercial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A
0
A
16
I/O
0
- I/O
7
O
WE
OE
CS
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
•
•
•
ADDRESS
C
E
•
•
•
1,048,576-BIT
MEMORY ARRAY
DECODER
8
O R
O
F
8
I/O CONTROL
8
CONTROL
LOGIC
3484 drw 01
AUGUST 2000
1
©2000 Integrated Device Technology, Inc.
DSC-3484/05
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
