IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
V
DD
V
SS
I/O 2
I/O 3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
I/O 4
A14
A13
A12
A11
A10
NC
3622 drw 02
Pin Configuration
NC
NC
A0
A1
A2
A3
A4
CS
I/00
I/01
V
DD
V
SS
I/02
I/03
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/07
I/06
V
SS
V
DD
I/05
I/04
A14
A13
A12
A11
A10
NC
NC
NC
SO36-1
SOJ
Top View
TSOP
Top View
Pin Description
A
0
– A
18
CS
WE
OE
I/O
0
- I/O
7
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
I/O
Power
Gnd
3622 tbl 02
3622 drw 11
Capacitance
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
8
Unit
pF
pF
3622 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Truth Table
(1,2)
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Output Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
3622 tbl 01
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
DD
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
6.42
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
