IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
t
AA
OE
tOE
(5)
tOLZ
CS
(3)
tACS
(5)
(5)
tOHZ
tCLZ
(5)
CHZ
t
HIGH IMPEDANCE
DATAOUT
DATAOUT VALID
t
PD
t
PU
I
I
CC
SB
V
CC SUPPLY
CURRENT
3622 drw 06
Timing Waveform of Read Cycle No. 2(1, 2, 4)
t
RC
ADDRESS
DATAOUT
tAA
t
OH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
3622 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
