IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
WCLK
t
DS
D
0
- D
17
t
ENS
D
0 (first valid write)
D
1
D
2
D
3
D
4
t
FRL(1)
t
SKEW2
RCLK
t
REF
t
ENS
t
A
Q
0
- Q
17
t
OLZ
t
OE
D
0
t
A
D
1
NOTES:
1. When t
SKEW2
minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW2
< minimum specification, t
FRL
(maximum) = either
2*t
CLK
+ t
SKEW2 or
t
CLK
+ t
SKEW2
. The Latency Timing applies only at the Empty Boundary (
EF
= LOW).
2. The first word is available the cycle after
EF
goes HIGH, always.
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
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NO WRITE
NO WRITE
WCLK
t
SKEW1
D
0
- D
17
(1)
t
DS
DATA WRITE
t
WFF
t
WFF
t
SKEW1
(1)
t
DS
DATA
WRITE
t
WFF
RCLK
t
ENS
t
ENH
t
ENS
t
ENH
LOW
t
A
Q
0
- Q
17
DATA IN OUTPUT REGISTER
DATA READ
t
A
NEXT DATA READ
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NOTE:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF
will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
FF
may not change state until the next WCLK edge.
Figure 8. Full Flag Timing
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
