IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
OPERATING CONFIGURATIONS
512/1,024/2,048/4,096 words or less. These FIFOs are in a
single Device Configuration when the First Load (FL), Write
ExpansionIn(WXI)andReadExpansionIn(RXI) controlinputs
are grounded (Figure 19).
SINGLE DEVICE CONFIGURATION
AsingleIDT72205LB/72215LB/72225LB/72235LB/72245LB
may be used when the application requirements are for 256/
RESET (
)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE (
LOAD (
)
READ ENABLE (
)
)
OUTPUT ENABLE (
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
DATA IN (D
0
- D17
)
DATA OUT (Q
0
- Q17
)
FULL FLAG (
)
EMPTY FLAG (
)
PROGRAMMABLE (
HALF-FULL FLAG (
)
PROGRAMMABLE (
)
)
2766 drw 21
READ EXPANSION IN (
WRITE EXPANSION IN (
)
FIRST LOAD (
)
)
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
user must create composite flags by ANDing the Empty Flags
of every FIFO, and separately ANDing all Full Flags. Figure 20
demonstratesa36-wordwidthbyusingtwoIDT72205B/72215B/
72225B/72235B/72245Bs. Any word width can be attained by
adding additional IDT72205B/72215B/72225B/72235B/
72245Bs. Please see the Application Note AN-83.
Wordwidthmaybeincreasedsimplybyconnectingtogether
the control signals of multiple devices. Status flags can be
detected from any one device. The exceptions are the Empty
Flag and Full Flag. Because of variations in skew between
RCLKandWCLK,itispossibleforflagassertionanddeassertion
to vary by one cycle between FIFOs. To avoid problems the
RESET (
)
RESET (
)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (
LOAD (
READ ENABLE (
OUTPUT ENABLE (
PROGRAMMABLE (
)
)
)
)
)
72205LB
72215LB
72225LB
72235LB
72245LB
PROGRAMMABLE (
HALF FULL FLAG (
)
72205LB
72215LB
72225LB
72235LB
72245LB
)
EMPTY FLAG (
)
18
DATA OUT (Q)
36
FULL FLAG (
)
18
FIRST LOAD (
WRITE EXPANSION IN (
READ EXPANSION IN (
)
2766 drw 22
)
)
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
14
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
