IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
WCLK
t
DS
D
0
- D
17
t
ENS
DATA WRITE 1
t
ENH
(1)
t
DS
DATA WRITE 2
t
ENS
t
ENH
t
FRL
t
SKEW2
t
REF
t
REF
t
REF
(1)
t
SKEW2
RCLK
t
FRL
LOW
t
A
Q
0
- Q
17
DATA IN OUTPUT REGISTER
DATA READ
2766 drw 11
NOTE:
1. When t
SKEW2
minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2.
When t
SKEW2
< minimum specification, t
FRL
(maximum) = either 2 * t
CLK
+ t
SKEW2,
or
t
CLK
+ t
SKEW2.
The Latency Timing apply only at the Empty Boundary (
EF
= LOW).
Figure 9. Empty Flag Timing
t
CLK
t
CLKH
WCLK
t
ENS
LD
t
ENS
WEN
t
DS
D
0
–D
15
PAE OFFSET
PAF OFFSET
D
0
–D
11
2766 drw 12
t
CLKL
t
ENH
t
DH
PAE OFFSET
Figure 10. Write Programmable Registers
t
CLKH
RCLK
t
CLK
t
CLKL
t
ENS
t
ENH
t
ENS
t
A
Q
0
–Q
15
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
2766 drw 13
Figure 11. Read Programmable Registers
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
