IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
t
CLK
t
CLKH
WCLK
t
DS
D
0
- D
17
DATA IN VALID
t
CLKL
t
DH
t
ENH
t
ENS
NO OPERATION
t
WFF
t
WFF
t
SKEW1(1)
RCLK
2766 drw 07
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF
will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
FF
may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
t
CLK
t
CLKH
RCLK
t
ENS
t
ENH
NO OPERATION
t
CLKL
t
REF
t
A
Q
0
- Q
17
t
OLZ
t
OE
t
SKEW2
WCLK
(1)
t
REF
VALID DATA
t
OHZ
2766 drw 08
NOTE:
1. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF
will go HIGH during the current clock cycle. If the
time between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then
EF
may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
