IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER 5 FORMAT
Bit
0
1
2
3
4
5
7-6
Function
Select Port B Interface
R
B
and
W
B
or
DS
B
and R/
W
B
Unused
Full Flag Definition
Empty Flag Definition
REQ Pin Polarity
ACK Pin Polarity
REQ / ACK Timing
0
1
0
1
0
1
0
1
00
01
10
11
8
9
10
11
12
13
14
15
Port B Read & Write
Timing Control for Peripheral Mode
Internal Clock
Frequency Control
Port B Interface
Mode Control
Unused
Unused
Unused
Unused
Unused
2668 tbl 12
0
1
Pins are
DS
B
and R/
W
B
(Motorola-style interface)
Pins are
R
B
and
W
B
(Intel-style interface)
Write pointer meets read pointer
Write pointer meets reread pointer
Read pointer meets write pointer
Read pointer meets rewrite pointer
REQ pin active HIGH
REQ pin active LOW
ACK pin active LOW
ACK pin active HIGH
2 internal clocks between REQ assertion and ACK assertion
3 internal clocks between REQ assertion and ACK assertion
4 internal clocks between REQ assertion and ACK assertion
5 internal clocks between REQ assertion and ACK assertion
0
1
0
1
0
1
R
B
,
W
B
, and
DS
B
are asserted for 1 internal clock
R
B
,
W
B
, and
DS
B
are asserted for 2 internal clocks
Internal clock = CLK
Internal clock = CLK divided by 2
Processor interface mode (Port B controls are inputs)
Peripheral interface mode (Port B controls are outputs)
Table 10. BiFIFO Configuration Register 5 Format
CONFIGURATION REGISTER 6 FORMAT
15
Unused
6
5
PIO5
4
PIO4
3
PIO3
2
PIO2
1
PIO1
0
PIO0
2668 tbl 13
Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data
CONFIGURATION REGISTER 7 FORMAT
15
Unused
6
5
MIO5
4
MIO4
3
MIO3
2
MIO2
1
MIO1
0
MIO0
2668 tbl 14
Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask
5.32
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
