72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
t
CLK
t
CLKH
WCLKA (WCLKB)
t
DH
t
DS
(DA
0
- DA
8
DB
0
- DB
8
)
DATA IN VALID
(
WENB1
)
t
ENS
t
ENH
NO OPERATION
t
CLKL
WENA1
WENA2 (WENB2)
(If Applicable)
t
WFF
(
FFB
)
t
SKEW1(1)
RCLKA (RCLKB)
t
WFF
NO OPERATION
FFA
RENA1
,
RENA2
(
RENB1
,
RENB2)
3034 drw 07
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for
FFA
(
FFB
) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
SKEW1
, then
FFA
(
FFB
) may not change
state until the next WCLKA (WCLKB) edge.
Figure 5. Write Cycle Timing
5.15
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
