72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
LDA WENA1
LDB WENB1
0
0
WCLKA
(1)
WCLKB
(1)
OPERATION ON FIFO A
OPERATION ON FIFO B
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
NOTE:
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1. The same selection sequence applies to reading from the registers.
RENA1
and
RENA2
(
RENB1
and
RENB2
) are enabled and read is per-
formed on the LOW-to-HIGH transition of RCLKA (RCLKB).
Figure 2. Writing to Offset Registers for FIFOs A and B
If FIFO A (B) is configured to have programmable flags,
when the
WENA1
(
WENB1
) and WENA2/
LDA
(WENB2/
LDB
)
are set LOW, data on the DA (DB) inputs are written into the
Empty (Least Significant Bit) offset register on the first LOW-
to-HIGH transition of the WCLKA (WCLKB). Data are written
into the Empty (Most Significant Bit) offset register on the
second LOW-to-HIGH transition of WCLKA (WCLKB), into
the Full (Least Significant Bit) offset register on the third
transition, and into the Full (Most Significant Bit) offset register
on the fourth transition. The fifth transition of WCLKA (WCLKB)
again writes to the Empty (Least Significant Bit) offset register.
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing
LDA
(
LDB
) HIGH, FIFO A (B) is returned to normal
read/write operation. When
LDA
(
LDB
) is set LOW, and
WENA1
(
WENB1
) is LOW, the next offset register in sequence is
written.
The contents of the offset registers can be read on the QA
(QB) outputs when WENA2/
LDA
(WENB2/
LDB
) is set LOW
and both Read Enables
RENA1
,
RENA2
(
RENB1
,
RENB2
) are
set LOW. Data can be read on the LOW-to-HIGH transition of
the read clock RCLKA (RCLKB).
A read and write should not be performed simultaneously
to the offset registers.
72801 - 256 x 9 x 2
8
7
Empty Offset (LSB) Reg.
Default Value 007H
8
0
8
0
8
7
72811 - 512 x 9 x 2
0
Empty Offset (LSB)
Default Value 007H
1
(MSB)
0
0
8
8
7
72821 - 1024 x 9 x 2
0
Empty Offset (LSB) Reg.
Default Value 007H
1
(MSB)
00
0
8
7
Full Offset (LSB) Reg.
Default Value 007H
0
(MSB)
0
8
1
(MSB)
00
0
0
0
8
7
Full Offset (LSB) Reg.
Default Value 007H
0
8
7
Full Offset (LSB)
Default Value 007H
8
0
8
1
72831 - 2048 x 9 x 2
8
7
Empty Offset (LSB) Reg.
Default Value 007H
8
2
(MSB)
000
8
7
Full Offset (LSB) Reg.
Default Value 007H
8
2
(MSB)
000
0
8
0
8
7
0
8
0
8
7
72841 - 4096 x 9 x 2
0
Empty Offset (LSB)
Default Value 007H
3
(MSB)
0000
0
Full Offset (LSB)
Default Value 007H
3
(MSB)
0000
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0
0
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
5.15
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
