IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D
0
–D
17
MRS
Name
Data Inputs
Master Reset
I/O
I
I
Description
Data inputs for a 18-bit bus.
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program
mable flag default settings, and serial or parallel programming of the offset settings.
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmable flag settings are all retained.
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the
EF
flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings.
RT
is useful to reread data from the first
physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
this pin functions as a serial input for loading offset registers
When enabled by
WEN,
the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by
SEN,
the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN,
the rising edge of RCLK reads data from the FIFO memory and offsetsfrom
the programmable registers.
REN
enables RCLK for reading data from the FIFO memory and offset registers.
OE
controls the output impedance of Q
n.
SEN
enables serial loading of programmable flag offsets.
During Master Reset,
LD
selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
This pin must be tied to either V
CC
or GND and must not toggle after Master Reset.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO
memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not
there is space available for writing to the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO
memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is
valid data available at the outputs.
PAF
goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
+3.3 Volt power supply pins.
Ground pins.
PRS
Partial Reset
I
RT
Retransmit
I
FWFT/SI
WCLK
First Word Fall
Through/Serial In
Write Clock
I
I
WEN
RCLK
REN
OE
SEN
LD
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
I
I
DC
FF/IR
Don't Care
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
Programmable
Almost-Empty Flag
Half-Full Flag
Data Outputs
Power
Ground
I
O
EF/OR
O
PAF
O
PAE
O
HF
Q
0
–Q
17
V
CC
GND
O
O
4
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
