IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
NO WRITE
WCLK
t
SKEW1
D
0
- D
8
t
WFF
FF
t
ENS
WEN1
t
ENS
WEN2
(If Applicable)
t
ENH
t
ENH
t
WFF
t
DS
NO WRITE
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
t
SKEW1
t
WFF
t
ENS
(1)
t
ENS
(1)
RCLK
t
ENS
t
ENH
t
ENS
t
ENH
REN1,
REN2
OE
LOW
t
A
t
A
Q
0
- Q
8
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2655 drw 10
NOTE:
1. Only one of the two write enable inputs,
WEN1
or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLK
t
DS
D
0
- D
8
t
ENS
WEN1
t
ENS
WEN2
(If Applicable)
t
SKEW1
RCLK
t
REF
EF
REN1,
REN2
OE
LOW
t
A
Q
0
- Q
8
DATA IN OUTPUT REGISTER
NOTE:
1. When t
SKEW1
≥
minimum specification, t
FRL
maximum = t
CLK
+ t
SKEW1
When
t
SKEW1
<
minimum specification, t
FRL
maximum = 2t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
t
DS
DATA WRITE 1
t
ENH
t
ENS
DATA WRITE 2
t
ENH
t
ENH
t
ENS
t
ENH
t
FRL
(1)
t
SKEW1
t
FFL
(1)
t
REF
t
REF
DATA READ
2655 drw 11
Figure 9. Empty Flag Timing
10