IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set LOW and both Read Enables (REN1,
REN2)
are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
IDT72421 - 64 x 9-BIT
8
6 5
0
Empty Offset (LSB) Reg.
Default Value 007H
8
0
8
8
IDT72201 - 256 x 9-BIT
7
Empty Offset (LSB) Reg.
Default Value 007H
0
0
8
6 5
Full Offset (LSB) Reg.
Default Value 007H
0
8
7
Full Offset (LSB) Reg.
Default Value 007H
0
8
0
8
0
IDT72211 - 512 x 9-BIT
8
7
Empty Offset (LSB)
Default Value 007H
8
1
(MSB)
0
8
7
Full Offset (LSB)
Default Value 007H
8
1
(MSB)
0
0
8
0
8
0
8
0
8
IDT72221 - 1,024 x 9-BIT
7
Empty Offset (LSB) Reg.
Default Value 007H
1
(MSB)
00
7
Full Offset (LSB) Reg.
Default Value 007H
1
(MSB)
00
0
0
0
0
IDT72231 - 2,048 x 9-BIT
8
7
Empty Offset (LSB) Reg.
Default Value 007H
8
2
(MSB)
000
8
7
Full Offset (LSB) Reg.
Default Value 007H
8
2
(MSB)
000
0
8
0
8
0
8
0
8
IDT72241 - 4,096 x 9-BIT
7
Empty Offset (LSB)
Default Value 007H
3
(MSB)
0000
7
Full Offset (LSB)
Default Value 007H
3
(MSB)
0000
0
8
0
8
0
8
0
8
IDT72251 8,192 x 9-BIT
7
Empty Offset (LSB)
Default Value 007H
4
(MSB)
00000
7
Full Offset (LSB)
Default Value 007H
4
(MSB)
00000
2655 drw 05
0
0
0
0
Figure 3. Offset Register Location and Default Values
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
