IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
17 16 15 14 13 12 11 10 9 8 7 6
D/Q0
Non-Interspersed
Parity
Interspersed
Parity
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
# of Bits Used:
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
17
16 15 14 13 12 11 10 9
5 4 3 2 1
8 7 6 5 4 3 2 1
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Non-Interspersed
Parity
Interspersed
Parity
17
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
# of Bits Used
IDT72V3640/50/60/70/80/90/100/110
x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
Non-Interspersed
Parity
Interspersed
Parity
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
EMPTY OFFSET (MSB) REGISTER (PAE)
17
17
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
2nd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
3rd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER (PAF)
17
17
D/Q0
IDT72V3640/50/60/70/80/90/100
x18 Bus Width
IDT72V36110
x18 Bus Width
4667 drw 07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
