IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
I/O
Description
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
I
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero
latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PRS
Partial Reset
I
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the
existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained.
RT
Retransmit
I
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the
EF
flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings.
RT
is useful to reread data from the first physical location of the FIFO.
FWFT/SI First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
Through/Serial In
functions as a serial input for loading offset registers.
OW
(1)
Output Width
I
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
(1)
IW
Input Width
I
This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
(1)
Bus-Matching
I
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
BM
BE
(1)
Big-Endian/
I
During Master Reset, a LOW on
BE
will select Big-Endian operation. A HIGH on
BE
during Master Reset
Little-Endian
will select Little-Endian format.
(1)
RM
Retransmit Timing I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normal latency mode.
PFM
(1)
Programmable
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode
will select Synchronous Programmable flag timing mode.
IP
(1)
Interspersed Parity I
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect
the data written to and read from the FIFO.
I
During Master Reset, this input along with FSEL1 and the
LD
pin, will select the default offset values for the programmable
FSEL0
(1)
Flag Select Bit 0
flags
PAE
and
PAF.
There are up to eight possible settings available.
(1)
Flag Select Bit 1
I
During Master Reset, this input along with FSEL0 and the
LD
pin will select the default offset values for the programmable
FSEL1
flags
PAE
and
PAF.
There are up to eight possible settings available.
WCLK
Write Clock
I
When enabled by
WEN,
the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers
for parallel programming, and when enabled by
SEN,
the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
Write Enable
I
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by
REN,
the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable
registers.
REN
Read Enable
I
REN
enables RCLK for reading data from the FIFO memory and offset registers.
OE
Output Enable
I
OE
controls the output impedance of Q
n.
SEN
Serial Enable
I
SEN
enables serial loading of programmable flag offsets.
LD
Load
I
This is a dual purpose pin. During Master Reset, the state of the
LD
input along with FSEL0 and FSEL1, determines
one of eight default offset values for the
PAE
and
PAF
flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
FF/IR
Full Flag/
O In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or Input Ready not the FIFO memory
is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing
to the FIFO memory.
EF/OR
Empty Flag/
O In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is empty.
Output Ready
In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the outputs.
PAF
Programmable
O
PAF
goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register.
PAF
goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PAE
Programmable
O
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register.
PAE
goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HF
Half-Full Flag
O
HF
indicates whether the FIFO memory is more or less than half-full.
O Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
Q
0
–Q
35
Data Outputs
state. Outputs are not 5V tolerant regardless of the state of
OE.
NOTE:
1. Inputs should not change state after Master Reset.
Symbol
D
0
–D
35
MRS
Name
Data Inputs
Master Reset
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
