IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for t
CLK
= 10ns, 15 ns
Output Load for t
CLK
= 7.5ns
NOTE:
1. For 133MHz operation input rise/fall times are 1.5ns.
AC TEST LOADS - 7.5ns Speed Grade
GND to 3.0V
3ns
(1)
1.5V
1.5V
See Figure 2a
See Figure 2b & 2c
1.5V
50
Ω
I/O
Z
0
= 50
Ω
4667 drw04a
Figure 2b. AC Test Load
AC TEST LOADS - 10ns, 15ns Speed Grades
3.3V
330Ω
D.U.T.
510Ω
30pF*
4667 drw04
6
5
t
CD
(Typical, ns)
4
3
2
1
20 30 50
80 100
Capacitance (pF)
200
4667 drw04b
Figure 2a. Output Load
* Includes jig and scope capacitances.
Figure 2c. Lumped Capacitive Load, Typical Derating
8
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