IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
50Ω TO V
CC
/2, CL = 20PF
V
CC
V
CC
V
CC
ENABLE AND DISABLE TEST CIRCUIT
6.0V
100
Ω
V
IN
Pulse
Generator
R
T
D.U.T.
20pF
100
Ω
C
L
R
T
3052 drw 05
V
OUT
V
IN
Pulse
Generator
D.U.T.
500Ω
V
OUT
GND
500Ω
3052 drw 06
PROPAGATION DELAY, OUTPUT SKEW
SYNC INPUT
(SYNC (1) or
SYNC (0))
1.5V
t
PD
t CYCLE SYNC INPUT
V
CC/2
FEEDBACK
INPUT
V
CC/2
Q/2 OUTPUT
t SKEWALL
Q0-Q4
OUTPUTS
tCYCLE "Q" OUTPUTS
1.5V
Q5 OUTPUT
V
CC/2
2Q OUTPUT
3052 drw 08
t SKEWf
t SKEWr
t SKEWf
t SKEWr
V
CC/2
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the V
CC
/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as
±
deviation
around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
t
PZH
SWITCH
GND
1.5V
0V
3V
1.5V
t
PHZ
0.3V
V
OH
0V
3052 drw 07
SWITCH POSITION
3V
1.5V
0V
3V
0.3V
V
OL
DISABLE
t
PLZ
Test
Disable Low
Enable Low
Disable High
Enable High
Switch
6V
GND
3052 tbl 10
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: t
F
≤
2.5ns; t
R
≤
2.5ns
9.8
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
