欢迎访问ic37.com |
会员登录 免费注册
发布采购

IDT74FCT388915T100PY 参数 Datasheet PDF下载

IDT74FCT388915T100PY图片预览
型号: IDT74FCT388915T100PY
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V低偏移基于PLL的CMOS时钟驱动器( 3 -STATE ) [3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)]
分类和应用: 时钟驱动器
文件页数/大小: 11 页 / 149 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第3页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第4页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第5页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第6页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第7页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第9页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第10页浏览型号IDT74FCT388915T100PY的Datasheet PDF文件第11页  
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4,
Q5
) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
50 MHz signal
12.5 MHz feedback signal
HIGH
OE/RST Q5
FEEDBACK
LOW
12.5 MHz
input
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
3052 drw 09
25 MHz feedback signal
HIGH
OE/RST Q5
FEEDBACK
LOW
25 MHz
input
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
FQ_SEL
Q0
Q1
FCT388915T
Q4
50 MHz signal
2Q
Q/2
12.5 MHz
signal
25 MHz
"Q"
Clock
Outputs
Q3
Q2
PLL_EN
HIGH
3052 drw 10
Q4
2Q
Q/2
HIGH
Q3
FCT388915T
Q2
25 MHz
"Q"
Clock
Outputs
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Output Feedback
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
50 MHz feedback signal
HIGH
OE/RST Q5
FEEDBACK
Q4
2Q
Q/2
12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
LOW
50 MHz
input
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
3052 drw 11
Q3
FCT388915T
Q2
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
9.8
8