RC64474™ RC64475™
Serial
Bit
255:18
17:15
Reserved
Description
Must be 0
000
→
0 cycles
001
→
1 cycle
010
→
2 cycles
011
→
3 cycles
100
→
4 cycles
101
→
5 cycles
110
→
6 cycles
111
→
7 cycles
Value & Mode Setting
WAdrWData_Del
Write address to write data delay in Master-
Clock cycles.®
14:13
Drv_Out
output driver slew rate control.
Bit 14 is MSB.
Affects only non-clock outputs.
Output driver strength:
10
→
100% strength (fastest)
11
→
83% strength
00
→
67% strength
01
→
50% strength (slowest)
0
→
64-bit system interface
1
→
32-bit system interface
0
→
Enabled Timer Interrupt
1
→
Disabled Timer Interrupt
00
→
RC4x00 compatible
01
→
Reserved
10
→
Pipelined writes
11
→
Write re-issue
Clock multiplier:
0 Multiply by 2
1 Multiply by 3
2 Multiply by 4
3 Multiply by 5
4 Multiply by 6
5 Multiply by 7
6 Multiply by 8
7 Reserved
0
→
Little endian
1
→
Big endian
64-bit:
9:15 Reserved
8
→
dxxxdxxxdxxxdxxx
7
→
ddxxxxxxddxxxxxx
6
→
dxxdxxdxxdxx
5
→
ddxxxxddxxxx
4
→
ddxxxddxxx
3
→
dxdxdxdx
2
→
ddxxddxx
1
→
ddxddx
0
→
dddd
Must be zero
Table 3 Boot-time Mode Stream
32-bit:
9:15 Reserved
8
→
wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx
7
→
wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx
6
→
wxxwxxwxxwxxwxxwxxwxxwxx
5
→
wwxxxxwwxxxxwwxxxxwwxxxx
4
→
wwxxxwwxxxwwxxxwwxxx
3
→
wxwxwxwxwxwxwxwx
2
→
wwxxwwxxwwxxwwxx
1
→
wwxwwxwwxwwx
0
→Æ
wwwwwwww
12
11
10:9
System interface bus width
TmrIntEn
Disables the timer interrupt on Int*[5]
Non-block write
Selects non-block write type.
Bit 10 is MSB.
7:5
Clock
Multiplier
MasterClock is multiplied internally to gener-
ate PClock
8
4:1
EndBit
Specifies byte ordering
Writeback data rate
System interface data rate for block writes
only:
bit 4 is MSB
0
Reserved
5 of 25
April 10, 2001
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
