RC64474™ RC64475™
Pin Name Type
Description
NMI*
I
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Initialization Interface
V
CCOk
I
I
I
VCC is OK
When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum for more
than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization sequence.
ColdReset*
Reset*
Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with Mas-
terClock.
Reset
This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for a cold reset,
or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with MasterClock.
ModeClock
ModeIn
O
I
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.
Boot-mode data in
Serial boot-mode data input.
JTAG Interface
TDI
I
JTAG Data In
On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register, depending on the
TAP controller state.
TDO
TCK
O
I
JTAG Data Out
On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When no data is
shifted out, the TDO is tri-stated (high impedance).
JTAG Clock Input
An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the system and pro-
cessor clock with nominal 40-60% duty cycle.
TMS
TRST*
I
JTAG Command Select
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on
the rising edge of TCK.
I
JTAG Reset
The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the processor logic.
During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this active low pin.
When asserted low, this pin will also tristate the TDO pin.
JTAG32*
JR_Vcc
I
I
JTAG 32-bit scan
This pin is used to control length of the scan chain for SYsAD (32-bit or 64-bit) for the JTAG mode. When set to Vss, 32-bit
bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to Vcc, 64-bit bus mode is
selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in pull-down device to guarantee 32-bit
scan, if it is left uncovered.
JTAG VCC
This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing the TRst* pin.
When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset.
Table 5 Pin Descriptions (Page 2 of 2)
8 of 25
April 10, 2001
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
