IDT79R3052-25J 参数 Datasheet PDF下载

IDT79R3051/79R3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

Symbol

t1

t1a

t2

Signals

(1, 2, 3)

(T

C

= 0°C to +85°C, V

CC

= +5.0V

±5%)

20MHz

25MHz

Min.

5

6

4

Max.

—

—

—

33.33MHz

Min.

4

5

3

Max.

—

—

—

40MHz

Min.

3

4.5

3

Max.

—

—

—

Unit

ns

ns

ns

Min.

6

7

4

Max.

—

—

—

Description

Set-up to

SysClk

rising

Set-up to

SysClk

falling

Hold from

SysClk

rising

Hold from

SysClk

falling

Tri-state from

SysClk

rising

Driven from

SysClk

falling

Asserted from

SysClk

rising

Valid from

SysClk

rising

BusReq

,

Ack

,

BusError

,

RdCEn

,

A/D

BusReq

,

Ack

,

BusError

,

RdCEn

,

A/D

A/D, Addr, Diag, ALE,

Wr

Burst

/

WrNear

,

Rd

,

DataEn

A/D, Addr, Diag, ALE,

Wr

Burst

/

WrNear

,

Rd

,

DataEn

BusGnt

BusGnt

Wr

,

Rd

,

Burst

/

WrNear

, A/D

ALE

ALE

A/D

t2a

t3

t4

t5

t6

t7

t8

t9

t10

t11

t12

t14

t15

t16

t17

t18

t19

t20

t21

t22

t23

t24

t25

t26

t27

t28

t29

t30

t31

tsys

t32

t33

tderate

2

—

—

—

—

—

—

—

2

—

0

0

—

—

—

—

—

10

10

25

200

32

6

6

2.5

6

3

6

3

2*t22

—

10

10

8

8

5

4

4

—

15

—

—

7

6

12

10

12

—

—

250

—

—

—

—

—

—

—

—

—

2*t22

2

—

—

—

—

—

—

—

2

—

0

0

—

—

—

—

—

8

8

20

200

32

5

5

2.5

5

3

5

3

2*t22

—

10

10

7

7

5

4

4

—

15

—

—

6

6

11

10

11

—

—

250

—

—

—

—

—

—

—

—

—

2*t22

1

—

—

—

—

—

—

—

1.5

—

0

0

—

—

—

—

—

6.5

6.5

15

200

32

4

4

2.5

4

2

4

2

2*t22

—

10

10

6

6

4

3

3

—

13

—

—

5

5

10

9

10

—

—

250

—

—

—

—

—

—

—

—

—

2*t22

1

—

—

—

—

—

—

—

1.5

—

0

0

—

—

—

—

—

5.6

5.6

12.5

200

32

3

3

2.5

3

2

3

2

2*t22

—

10

10

5

5

3.5

3

3

—

12

—

—

4

4.5

9

8

9

—

—

250

—

—

—

—

—

—

—

—

—

2*t22

ns

ns

ns/

25pF

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

µs

tsys

ns

ns

ns

ns

ns

ns

ns

Negated from

SysClk

falling

Asserted from

SysClk

rising

Negated from

SysClk

falling

Hold from ALE negated

Asserted from

SysClk

falling

Asserted from A/D

tri-state

(4)

Driven from

SysClk

rising

(4)

Valid from

SysClk

Valid from

SysClk

DataEn

DataEn

A/D

Wr

,

Rd

,

DataEn

,

Burst

/

WrNear

Addr(3:2)

Diag

A/D

A/D

Clk2xIn

Clk2xIn

Clk2xIn

Negated from

SysClk

falling

Tri-state from

SysClk

falling

SysClk

falling to data out

Pulse Width HIGH

Pulse Width LOW

Clock Period

Pulse Width from Vcc valid

Minimum Pulse Width

Set-up to

SysClk

falling

Mode set-up to

Reset

rising

Set-up to

SysClk

falling

Set-up to

SysClk

falling

Pulse Width

Clock HIGH Time

Clock LOW Time

Timing deration for loading

over 25pf

(4, 5)

Reset

Reset

Reset

Int

Int

SInt

, SBrCond

SInt

, SBrCond

Int

, BrCond

Int

, BrCond

SysClk

SysClk

SysClk

All outputs

Mode hold from

Reset

rising

Hold from

SysClk

falling

Hold from

SysClk

falling

t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1

t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1

—

0.5

—

0.5

—

0.5

—

0.5

NOTES:

2874 tbl 08

1. All timings referenced to 1.5V, with a rise and fall time of less than 2.5ns.

2. All outputs tested with 25pF loading.

3. The AC values listed here reference timing diagrams contained in the R3051 Family Hardware User's Manual.

4. Guaranteed by design.

5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified

test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.

5.3

12