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IN74HC75AD 参数 Datasheet PDF下载

IN74HC75AD图片预览
型号: IN74HC75AD
PDF下载: 下载PDF文件 查看货源
内容描述: 双2位透明锁存器高性能硅栅CMOS [Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS]
分类和应用: 锁存器
文件页数/大小: 6 页 / 282 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN74HC75A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
125
25
21
110
22
19
145
29
25
125
25
21
75
15
13
10
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, D to Q (Figures 1
and 5)
Maximum Propagation Delay , D to Q
(Figures 1 and 5)
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Latch)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
155
31
26
140
28
24
180
36
31
155
31
26
95
19
16
10
190
38
32
165
33
28
220
44
38
190
38
32
110
22
19
10
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
35
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(C
L
=50pF, Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time,
Input D to Latch Enable
(Figure 4)
Minimum Hold Time,Latch
Enable to D (Figure 4)
Minimum Pulse Width, Latch
Enable Input
(Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
100
20
17
25
5
5
80
16
14
1000
500
400
Guaranteed Limit
≤85°C
125
25
21
30
6
6
100
20
17
1000
500
400
≤125°C
150
30
26
40
8
7
120
24
20
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r,
t
f
ns
Rev. 00