AC Electrical Characteristics † - Processor Bus (Figures 11 and 17)
1
2
3
4
5
6
7
8
9
10
11
12
13
Characteristics
Sym
Chip Select Setup Time
t
CSS
Read/Write Setup Time t
RWS
Address Setup Time
t
ADS
A
cknowledgement
Fast
t
AKD
Delay
Slow
t
AKD
Fast Write Data Setup Time
t
FWS
Slow Write Data Delay t
SWD
Read Data Setup Time
t
RDS
Data Hold Time Read
t
DHT
Write
t
DHT
Read Data To High Imp. t
RDZ
Chip Select Hold Time
t
CSH
Read/Write Hold Time
t
RWH
Address Hold Time
t
ADH
Acknow. Hold Time
t
AKH
Min
20
25
25
40
2.7
20
Typ ‡ Max
0
5
5
100
7.2
2.0
20
20
0
0
0
10
1.7
0.5
Units
ns
ns
ns
ns
cycles
ns
cycles
cycles
ns
ns
ns
ns
ns
ns
ns
Test Conditions
C
L
=150 pF
C4i cycles
➀
C4i cycles
➀
C4i cycles
➀,
C
L
= 150 pF
R
L
=1 KΩ * , C
L
=150 pF
R
L
=1 KΩ * , C
L
=150 pF
10
50
90
60
80
R
L
=1 KΩ * , C
L
=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.
➀
Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
Figure 17 Processor Bus
2.0V
0.8V
DS
CS
2.0V
0.8V
t
CSS
t
CSH
R/W
2.0V
0.8V
t
RWS
t
RWH
A5
to
A0
2.0V
0.8V
t
ADS
2.4V
0.4V
t
RDS
t
AKD
t
ADH
t
AKH
DTA
D7
to
D0
t
DHT
2.4V (Read) 2.0V (Write)
0.8V (Read) 0.8V (Write)
t
SWD
t
FWS
t
RDZ
11
IMP [ IMP, INC ]
