FZL 4146
Operating Range
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Supply voltage11)
Supply voltage12)
Supply voltage13)
Supply voltage rise
VS
VS
VS
dVS/dt
4.5
40
V
V
V
V/µs
V
V
TS = 0 … 1.5 V
TS = 1.5 … 7 V
VTS + 3 40
10
– 1
40
1
VTS = VS
20)
Junction temperature
Tj
– 25
1
150
100
°C
10)
Time-determining capacitor of
the clock generator
Ce
nF
14) 15) 16) 17) 19)
Input voltage
VDI, ENA, TS
ISQ
– 2
– 1
40
6
V
Current at output SQ
mA
9)
Notes:
W pins that remain open, must be connected to VS.
The Ce value depends on the desired pulse width tp during short circuit.
It applies: Ce = 0.25 mS x tp.
At an input threshold = 1.5 V
At an input threshold = 1.5 V to 7 V
At an input threshold = 7 V
10)
11)
12)
13)
14)
This function is also ensured for 40 V ≤ VS ≤ 45 V and – 40 °C ≤ Tj ≤ – 25 °C as long as
0 V ≤ VDI, ENA, TS ≤ 40 V.
15)
16)
17)
18)
19)
20)
The outputs Q are disabled even if – 3 V ≤ VDI, ENA ≤ – 2 V or – 1 mA ≤ IDI, ENA ≤ 50 µA and
VS – 5 V ≤ VW ≤ VS + 5 V, max. 45 V.
The outputs Q are enabled even if 40 V ≤ VDI, ENA ≤ 45 V and VS – 0.2 V ≤ VW ≤ VS + 5 V,
max. 45 V.
Current limiting and disabling of outputs Q are ensured even if 40 V ≤ VDI, ENA ≤ 45 V and
VS – 5 V ≤ VW ≤ VS – 0.4 V.
Dynamic charge reversal of a 2-nF capacitor as in figure 1 is permissible (corresponds
to short circuit to conducting output in P-channel MOSFET)
Proper working of the IC is also ensured if, before VS is turned-On, an input voltage
V
DI, ENA is present in the permissible range (footnote 15).
At 10 V/µs short-term malfunction is possible, but never a latch-up.
Semiconductor Group
8
INFINEON [ Infineon ]
