Functional Description
2.3
IOM®-1 Mode Functions
2.3.1
IOM®-1 Frame Structure / Timing Modes
This interface consists of one data line per direction (IOM Data Ports 0 and 1:IDP0, 1). Three
additional signals define the data clock (DCL) and the frame synchronization (FSC1/2) at this
interface. The data clock has a frequency of 512 kHz (twice the data rate) and the frame sync
clock has a repetition rate of 8 kHz.
Via this interface four octets are transmitted per 125 µs frame (figure 13). The first two octets
constitute the two 64 kbit/s B channels. In the ISAC-S the MONITOR channel (third octet)
serves:
– for arbitration of the access to the IOM-TIC bus on IDP1 in case several layer-2 components
are connected together (see chapter 2.3.9).
– to indicate the status on the S bus D channel (IDP0, bit 3 of the monitor octet), "stop/go"
(see chapter 2.5.7).
– for the exchange of data using the IOM-1 MONITOR channel protocol which involves the E
bit as data validation bit (see chapter 2.3.7).
Two bits in the fourth octet are used for the 16 kbit/s D channel. The controlling and monitoring
of layer-1 functions (activation/deactivation of the S interface...) is done via the Command/
Indication bits. The T bit is not used in ISAC-S IOM-1 applications.
125 µs
B1
B2
MONITOR
D
C / Ι
T E
TIC-Bus
ITD00852
Figure 13
IOM®-1 Frame Structure
IOM®-1 Timing
In TE mode the IOM timing is internally generated by DPLL circuitry from the S interface and
DCL and FSC 1/2 are outputs.
In LT-S, NT and LT-T modes the clock and frame synchronization signals are inputs.
The IOM interface can be operated either in timing mode 0 or in timing mode 1, selected by
SPM bit in SPCR register.
Semiconductor Group
40
INFINEON [ Infineon ]
